- 1 - e05465-ps this ic is esd sensitive device. s pecial handling precautions are required. sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or ot herwise under any patents or other right . application circuits shown, if any, are typical examples illu strating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXG1188UR high power dpdt switch with logic control description the CXG1188UR can be used in wireless communication systems, for example, cdma handsets with gps. the ic has on-chip logic for operat ion with 1 cmos control input. the sony j-fet process is used for low insertion loss and on-chip logic circuit. (applications: dual-band cellular handset s, cdma with gps, dual-band cdma) features ? low insertion loss: 0.30db@900mhz, 0.45db@1900mhz ? high linearity: iip3 = 65dbm (typ.) ? 1 cmos compatible control line package small package size: 12-pin uqfn structure gaas j-fet mmic absolute maximum ratings (ta = 25 c) ? bias voltage v dd 7v ? control voltage vctl 5 v ? operation temperature topr ?35 to +85 c ? storage temperature tstg ?65 to +150 c
CXG1188UR - 2 - block diagram and recommended circuit when using this ic, the followi ng external components should be used: c rf : this capacitor is used for rf decoupling and must be used for all applications. cbypass: this capacitor is used for dc line filtering. 100pf is recommended. truth table dc bias conditions (ta = 25 c) cbypass (100pf) c rf c rf rf1 gnd ctl gnd v dd gnd rf4 gnd gnd 10 9 7 1 3 11 12 f3 f1 f2 f4 gnd rf2 c rf rf3 c rf 8 2 6 5 4 ctl on state off state f1 f2 f3 f4 l rf1 ? rf2, rf3 ? rf4 rf2 ? rf3, rf4 ? rf1 on off on off h rf2 ? rf3, rf4 ? rf1 rf1 ? rf2, rf3 ? rf4 off on off on item min. typ. max. unit vctl (h) 2.0 3.0 3.6 v vctl (l) 0 ? 0.4 v v dd 2.7 3.0 3.6 v
CXG1188UR - 3 - electrical characteristics (ta = 25 c) *1 pin = 25dbm, 0/3v control, v dd = 3.0v, 900mhz *2 pin = 25dbm (900mhz) + 25dbm (901mhz), 0/3v control, v dd = 3.0v *3 pin = 25dbm, 0/3v control, v dd = 3.0v, 1.9ghz *4 pin = 25dbm (1.9ghz) + 25dbm (1.901ghz), 0/3v control, v dd = 3.0v pin description item symbol condition min. typ. max. unit insertion loss il 900mhz 0.30 0.55 db 1.9ghz 0.45 0.70 db isolation iso. 900mhz 18 21 db 1.9ghz 14 16 db vswr vswr 50 ? 1.2 ? harmonics 2fo *1 ?75 ?60 dbc *3 ?75 ?60 dbc 3fo *1 ?75 ?60 dbc *3 ?75 ?60 dbc input ip3 iip3 *2 55 65 dbm *4 55 65 dbm 1db compression input power p1db v dd = 2.8v 32 35 dbm switching speed tsw 1 5 s bias current i dd v dd = 3.0v 55 130 a control current ictl vctl (h) = 3.0v 40 100 a pin no. symbol description 1 gnd control signal input 2 rf1 rf signal input 3gnd gnd 4 rf2 rf signal output 5gnd gnd 6 rf3 rf signal input 7gnd gnd 8 rf4 rf signal output 9gnd gnd 10 v dd power supply input 11 gnd gnd 12 ctl control signal input
CXG1188UR - 4 - sony corporation package outline (unit: mm) pin 1 index c 0.1 s a-b 0.4 0.05 m s c c a-b s 0.05 s max0.02 + 0.09 12pin uqfn 9? plastic 9? 0.25 ? 0.03 + 0.09 0.14 ? 0.03 x 4 2.0 4 1 3 9 7 6 12 10 2.0 s 0.4 0.1 : 0.6 0.55 0.05 4-r0.2 a b 0.25 0.14 0.07 0.18 sony code eiaj code jedec code package material lead treatment lead material epoxy resin solder plating copper alloy 0.01g package structure uqfn-12p-01 package mass terminal section note:cutting burr of lead are 0.05mm max. solder plating thermal die pad lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec.
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